The present invention relates to a structure and a process for plating vias and lines and is particularly concerned with significantly reducing, if not entirely eliminating, void formation in the plating in the vias and lines. The present invention finds particular applicability in filling undercut features in interconnect and packaging structures.
AlCu and its related alloy are currently the predominately used conductors for forming interconnection from electronic devices such as integrated circuits. The amount of Cu in AlCu is typically in the range from about 0.3 to 4%.
Replacement of AlCu by Cu and Cu alloys as a chip interconnection material results in advantages of improved chip performance. Performances improved because the resistivity of Cu in certain copper alloys is less than the resistivity of AlCu. Besides performance, high chip yield count and higher circuit wiring density are also realized.
The advantages of copper metallization has been recognized by the entire semiconductor industry Copper metallization has been the subject of extensive research documented by two entire issues of the Materials Research Society (MRS) Bulletin when dedicated to academic research on this subject is MRS Bulletin, Vol. XVIII, No. 6 (June 1993) and the other dedicated to industrial research in MRS Bulletin, Vol. XIX, No. 8 (August 1994). A 1993 paper by Luther et al., Planar Copper-Polyamide Back End of the Line Interconnection for ULSI Devices, in Proc IEEE VLSI Multi-Level Interconnections Conference, Santa Clara, Calif., Jun. 8-9, 1993, page 15, describes the fabrication of copper chip interconnections with four levels of metallization.
Processes such as chemical vapor deposition (CVD) and electroless plating are popular methods for depositing copper. Both methods of deposition normally produce at best conformal deposits and inevitably lead to defects (voids or seams) in wiring especially when trenches have a cross section narrower at the top then at the bottom. Other problems of CVD have been described by Li et al., copper-based metallization in ULSI structuresxe2x80x94Part II; Is Cu Ahead of its Time as an On-Chip Material?, MRSBULL., XIX, Vol. 15 (1994). In electroless plating, while offering the advantage of low cost, the evolution of hydrogen during metal deposition tends to lead to blistering and other defects that are viewed as weaknesses for industry-wide implementation.
Although, continuing work is being done to provide coating processes for fabricating low cost, highly reliable copper interconnect structures for wiring an integrated circuit chips with void-free seamless conductors of sub-micron dimensions, room for improvements still exists especially for filling vias that have an undercut feature.
The use of an undercut feature which may not be desirable; however, is desirable since it provides for a metal lock-in structure.
The present invention relates to a process for filling or plating vias and especially relates to significantly reducing, if not entirely eliminating, void formation in the filling in the vias. The present invention makes it possible to fabricate a low cost, highly reliable copper interconnect structure for wiring in integrated circuit chips with void-free seamless conductors of sub-micron dimension even in vias that include an undercut feature.
More particularly, the present invention includes providing a substrate having interconnect structures therein into which the conductor will be deposited to ultimately form lines or conductive vias. A electrically conductive seed layer or plating base layer is deposited in the vias. The electrically conductive interconnect in the vias is provided by electroplating from a bath containing an aliphatic amine alkoxylate surface active agent. The aliphatic amine alkoxylate is present in an amount sufficient to reduce void formation. The resulting structure can then be planarized or polished by chemical-mechanical polishing to thereby form individual lines and/or electrically conductive vias, electrically insulated from each other.
According to a further aspect of the present invention, an interconnect structure is provided on an electronic device by providing a substrate having interconnect structures therein, forming a conductive layer serving as a seed layer or plating base in the interconnect features, forming a patterned resist layer on the plating base, depositing the electrically conductor material by electroplating from a bath containing an aliphatic amine alkoxylate surface active agent in an amount sufficient to reduce void formation, and then removing the patterned photoresist. The bath also typically includes brightness and leveling agents.